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    EASE offers the best of both worlds with your choice of graphical or text based HDL entry. You don’t need to be a master of either Verilog or VHDL. When you’re creating a new design, just enter your design using your mix of graphics and text. EASE automatically generates optimized HDL code for you in the selected language – VHDL or Verilog. Industry standard version control environments deal with design and configuration management enabling multiple users to work simultaneously on one EASE project.

    Features & Benefits

    • Graphical design environment with automated generation of hierarchical VHDL or Verilog code
    • Standards compliant:
      – VHDL: IEEE-1076 87, 93 & 2008
      – Verilog: IEEE-1364 95, 2001
    • Virtual records to decrease diagram complexity and increase flexibility
    • True multi-user design environment and associated version control, managed by a sophisticated design environment browser
    • Push-button import of legacy Verilog or VHDL designs and extraction of graphical hierarchy
    • Integrates smoothly with the industry’s most popular simulators and synthesis tools
    • Platform independent database
    • Integrated HDL language editor
    • Hot error reporting